1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and methods for the formation thereof, and, more particularly, to integrated circuits including transistors that are adapted for operation at different voltages of operation and methods for the formation thereof.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements which include, in particular, field effect transistors. In a field effect transistor, a gate electrode is provided. The gate electrode may be separated from a channel region of the field effect transistor by a gate insulation layer that provides electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region that may be doped differently than the channel region are provided. Depending on an electric voltage applied to the gate electrode, the field effect transistor can be switched between an ON-state and an OFF-state, wherein an electrical conductivity of the channel region in the ON-state is greater than an electrical conductivity of the channel region in the OFF-state.
Field effect transistors in integrated circuits can include logic transistors, which can be adapted for operation at a relatively low voltage of operation. Logic transistors can be adapted for providing a relatively small threshold voltage, relatively small leakage currents and/or a relatively high switching speed.
In addition to logic transistors, integrated circuits can include other types of field effect transistors that are adapted for use at a higher voltage of operation than logic transistors. Such high-voltage transistors can include input/output transistors that are used for handling an input to and/or an output of the integrated circuit and/or power transistors such as, for example, lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors. Power transistors can be used, for example, in microwave and/or radio frequency amplifiers. In some applications, for example, radio frequency identification (RFID) tags and/or electrical components for use in mobile communication, it may be of advantage to provide both logic circuitry including logic transistors and microwave and/or radio frequency amplifiers including power transistors in the same integrated circuit.
For improving the performance of integrated circuits, it has been proposed to employ semiconductor-on-insulator technology. In semiconductor-on-insulator technology, a semiconductor-on-insulator structure is provided. The semiconductor-on-insulator structure includes a thin layer of semiconductor material, for example silicon, that is provided above a semiconductor substrate, for example a silicon wafer. The layer of semiconductor material is separated from the semiconductor substrate by a layer of electrically insulating material, for example silicon dioxide. Compared to integrated circuits wherein field effect transistors are formed on a bulk semiconductor substrate, semiconductor-on-insulator technology can allow reducing parasitic capacitances and leakage currents. Moreover, integrated circuits formed in accordance with semiconductor-on-insulator technology may be less sensitive with respect to ionizing radiation.
However, semiconductor-on-insulator technology can have some specific issues associated therewith, which include the so-called floating body effect. The body of a field effect transistor can form a capacitor with the insulated semiconductor substrate. In this capacitor, electric charge can accumulate and cause adverse effects, which may include a dependence of the threshold voltage of the field effect transistor on its previous states.
For substantially avoiding the floating body effect, it has been proposed to use fully depleted field effect transistors. Fully depleted field effect transistors are formed using a semiconductor-on-insulator structure, wherein the layer of semiconductor material provided on the electrically insulating layer has a smaller thickness than a channel depletion depth of the field effect transistor. Thus, the electric charge and, accordingly, the body potential of the field effect transistor can be fixed.
While fully depleted semiconductor-on-insulator technology can be of advantage for logic transistors, integrating fully-depleted logic transistors and high-voltage transistors in a same integrated circuit can have some issues associated therewith. Approaches according to the state of the art include providing LDMOS transistors in areas of a semiconductor structure wherein the layer of electrically insulating material and the layer of semiconductor material of the semiconductor-on-insulator structure are removed. Thus, LDMOS transistors can be provided in the form of bulk transistors. However, such approaches can require a relatively complicated processing.
Other approaches according to the state of the art include forming input/output transistors in accordance with semiconductor-on-insulator technology, wherein the input/output transistors include a thicker gate dielectric (which may be formed, for example, from silicon oxynitride) than the logic transistors. The logic transistors may include a relatively thin gate dielectric formed of a high-k material. However, the ability of such input/output transistors to withstand high voltages of operation may be limited.
Further approaches according to the state of the art include forming source, channel and drain regions of input/output transistors in the semiconductor substrate of the semiconductor-on-insulator structure and forming gate structures of the input/output transistors from the layer of electrically insulating material and the layer of semiconductor material of the semiconductor-on-insulator structure. In such approaches, the layer of electrically insulating material of the semiconductor-on-insulator structure can provide a gate insulation layer of the input/output transistors, and a gate electrode of the input/output transistors can be formed from the layer of semiconductor material of the semiconductor-on-insulator structure. However, the layout of such input/output transistors can differ substantially from classical transistor layouts, which may adversely affect the reliability of the transistors.
In view of the situation described above, the present disclosure relates to methods and systems that can help to avoid or at least reduce some or all of the above-mentioned issues.